GTX 580 Memory Controller Configuration Technical Question
Does anyone know the exact configuration and latencies for the GTX 500 series (Specifically the 580) memory controllers?

All I can find is that there are 6x 64bit memory controllers -- But how many clock cycles does a memory access take and is it 6 controllers per SM or for the entire card? Are some disabled on lower end cards for yield/X excuse?

Please note I don't actually own a graphics card -- of any description. I'm writing an essay for school on optimisation but cannot find the penalties for cache misses (IE memory accesses)

I've already read the Fermi whitepaper & GTX580 datasheet (Which had nothing you'd expect to find on a normal data sheet :\):
http://www.nvidia.com/content/PDF/fermi_white_papers/NVIDIA_Fermi_Compute_Architecture_Whitepaper.pdf
http://www.geforce.com/Active/en_US/en_US/pdf/GTX-580-Web-Datasheet-Final.pdf
Does anyone know the exact configuration and latencies for the GTX 500 series (Specifically the 580) memory controllers?



All I can find is that there are 6x 64bit memory controllers -- But how many clock cycles does a memory access take and is it 6 controllers per SM or for the entire card? Are some disabled on lower end cards for yield/X excuse?



Please note I don't actually own a graphics card -- of any description. I'm writing an essay for school on optimisation but cannot find the penalties for cache misses (IE memory accesses)



I've already read the Fermi whitepaper & GTX580 datasheet (Which had nothing you'd expect to find on a normal data sheet :\):

http://www.nvidia.com/content/PDF/fermi_white_papers/NVIDIA_Fermi_Compute_Architecture_Whitepaper.pdf

http://www.geforce.com/Active/en_US/en_US/pdf/GTX-580-Web-Datasheet-Final.pdf

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Dell Latitude XT2

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#1
Posted 01/30/2012 12:33 PM   
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